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1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl2110, ISL2111 100v, 3a/4a peak, high frequency half-bridge drivers the isl2110, ISL2111 are 100v, high frequency, half-bridge n-channel power mosfet driver ics. they are based on the popular hip2100, hip2101 hal f-bridge drivers, but offer several performance improvements. peak output pull-up/ pull-down current has been increased to 3a/4a, which significantly reduces switching power losses and eliminates the need for external totem-pole buffers in many applications. also, the low end of the v dd operational supply range has been extended to 8vdc. the isl2110 has additional input hysteresis for superior operation in noisy environments and the inputs of the ISL2111, like those of the isl2110, can now safely swing to the v dd supply rail. features ? drives n-channel mosfet half-bridge ? soic and dfn package options ? soic and dfn packages comp liant with 100v conductor spacing guidelines per ipc-2221 ? pb-free plus anneal available (rohs compliant) ? bootstrap supply max voltage to 114vdc ? on-chip 1 ? bootstrap diode ? fast propagation times for multi-mhz circuits ? drives 1nf load with typical rise/fall times of 9ns/7.5ns ? cmos compatible input thresholds (isl2110) ? 3.3v/ttl compatible input thresholds (ISL2111) ? independent inputs provide flexibility ? no start-up problems ? outputs unaffected by supply glitches, hs ringing below ground or hs slewing at high dv/dt ? low power consumption ? wide supply voltage range (8v to 14v) ? supply undervoltage protection ?1.6 ?/ 1 ? typical output pull-up/pull-down resistance applications ? telecom half-bridge dc/dc converters ? telecom full-bridge dc/dc converters ? two-switch forward converters ? active-clamp forward converters ? class-d audio amplifiers ordering information part number (notes 1, 2) part marking temp. range (c) package (pb-free) pkg. dwg. # isl2110abz 2110abz -40 to 125 8 ld soic m8.15 isl2110ar4z 2110ar4z -40 to 125 12 ld 4x4 dfn l12.4x4a ISL2111abz 2111abz -40 to 125 8 ld soic m8.15 ISL2111ar4z 2111ar4z -40 to 125 12 ld 4x4 dfn l12.4x4a notes: 1. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination fini sh, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. add ?-t? suffix for tape and reel packing option. pinouts isl2110, ISL2111 (soic) top view isl2110, ISL2111 (dfn) top view note: epad = exposed pad. 5 6 8 7 4 3 2 1 v dd hb ho hs lo li hi v ss v dd nc nc hb ho lo v ss nc nc li hs hi 2 3 4 1 5 11 10 9 12 8 6 7 epad data sheet july 11, 2006 fn6295.1
2 fn6295.1 july 11, 2006 application block diagram functional block diagram secondary circuit +100v control controller pwm li hi ho lo v dd hs hb +12v v ss reference and isolation drive lo drive hi isl2110 ISL2111 under voltage v dd hi li v ss driver driver hb ho hs lo level shift under voltage epad (dfn package only) ISL2111 ISL2111 *epad = exposed pad. the epad is electric ally isolated from all other pins. for best thermal performance connect the epad to the pcb power ground plane. isl2110, ISL2111
3 fn6295.1 july 11, 2006 secondary isolation pwm +48v +12v circuit figure 1. two-switch forward converter isl2110 ISL2111 secondary circuit isolation pwm +48v +12v figure 2. forward converter with an active-clamp isl2110 ISL2111 isl2110, ISL2111
4 fn6295.1 july 11, 2006 absolute maximum rati ngs thermal information supply voltage, v dd, v hb - v hs (notes 3, 4) . . . . . . . . -0.3v to 18v li and hi voltages (note 4) . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v voltage on lo (note 4) . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v voltage on ho (note 4) . . . . . . . . . . . . . . v hs - 0.3v to v hb + 0.3v voltage on hs (continuous) (note 4) . . . . . . . . . . . . . . -1v to 110v voltage on hb (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118v average current in v dd to hb diode . . . . . . . . . . . . . . . . . . 100ma maximum recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 14v voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 100v voltage on hs . . . . . . . . . . . . . . .(repetitive transient) -5v to 105v voltage on hb . . v hs + 7v to v hs + 14v and v dd - 1v to v dd + 100v hs slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50v/ns thermal resistance (typical) ja (c/w) jc (c/w) soic (note 5) . . . . . . . . . . . . . . . . . . . 95 n/a dfn (note 6) . . . . . . . . . . . . . . . . . . . . 40 3 max power dissipation at 25c in free air (soic, note 5) . . . . 1.3w max power dissipation at 25c in free air (dfn, note 6) . . . . . 3.1w storage temperature range . . . . . . . . . . . . . . . . . . . -65c to 150c junction temperature range. . . . . . . . . . . . . . . . . . . -55c to 150c lead temperature (soldering 10s - soic lead tips only) . . . 300c for recommended soldering conditions see tech brief tb389. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditio ns of this specification is not implied. notes: 3. the isl2110 and ISL2111 are capable of derated operation at s upply voltages exceeding 14v. figure 22 shows the high-side volt age derating curve for this mode of operation. 4. all voltages referenced to v ss unless otherwise specified. 5. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board. see tech brief tb379 f or details. 6. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. for jc, the ?case temp? is measured at the center of the exposed meta l pad on the package underside. see tech brief tb379 for details. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameters symbol test conditions t j = 25c t j = -40c to 125c units min typ max min max supply currents v dd quiescent current i dd isl2110; li = hi = 0v - 0.1 0.25 - 0.3 ma v dd quiescent current i dd ISL2111; li = hi = 0v - 0.3 0.45 - 0.55 ma v dd operating current i ddo isl2110; f = 500khz - 3.4 5.0 - 5.5 ma v dd operating current i ddo ISL2111; f = 500khz - 3.5 5.0 - 5.5 ma total hb quiescent current i hb li = hi = 0v - 0.1 0.15 - 0.2 ma total hb operating current i hbo f = 500khz - 3.4 5.0 - 5.5 ma hb to v ss current, quiescent i hbs li = hi = 0v; v hb = v hs = 114v - 0.05 1.5 - 10 a hb to v ss current, operating i hbso f = 500khz; v hb = v hs = 114v - 1.2 - - - ma input pins low level input voltage threshold v il isl2110 3.7 4.4 - 3.5 - v low level input voltage threshold v il ISL2111 1.4 1.8 - 1.2 - v high level input voltage threshold v ih isl2110 - 6.6 7.4 - 7.6 v high level input voltage threshold v ih ISL2111 - 1.8 2.2 - 2.4 v input voltage hysteresis v ihys isl2110 - 2.2 - - - v input pull-down resistance r i - 210 - 100 500 k ? under voltage protection v dd rising threshold v ddr 6.1 6.6 7.1 5.8 7.4 v v dd threshold hysteresis v ddh -0.6---v isl2110, ISL2111
5 fn6295.1 july 11, 2006 hb rising threshold v hbr 5.5 6.1 6.8 5.0 7.1 v hb threshold hysteresis v hbh -0.6---v boot strap diode low current forward voltage v dl i vdd-hb = 100 a - 0.5 0.6 - 0.7 v high current forward voltage v dh i vdd-hb = 100ma - 0.7 0.9 - 1 v dynamic resistance r d i vdd-hb = 100ma - 0.7 1 - 1.5 ? lo gate driver low level output voltage v oll i lo = 100ma - 0.1 0.18 - 0.25 v high level output voltage v ohl i lo = -100ma, v ohl = v dd - v lo - 0.16 0.23 - 0.3 v peak pull-up current i ohl v lo = 0v -3---a peak pull-down current i oll v lo = 12v - 4 - - - a ho gate driver low level output voltage v olh i ho = 100ma - 0.1 0.18 - 0.25 v high level output voltage v ohh i ho = -100ma, v ohh = v hb - v ho - 0.16 0.23 - 0.3 v peak pull-up current i ohh v ho = 0v -3---a peak pull-down current i olh v ho = 12v - 4 - - - a electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified (continued) parameters symbol test conditions t j = 25c t j = -40c to 125c units min typ max min max switching specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameters symbol test conditions t j = 25c t j = -40c to 125c units min typ max min max lower turn-off propagation de lay (li falling to lo falling) t lphl - 32 50 - 60 ns upper turn-off propagation dela y (hi falling to ho falling) t hphl - 32 50 - 60 ns lower turn-on propagation delay (li rising to lo rising) t lplh - 39 50 - 60 ns upper turn-on propagation delay (hi rising to ho rising) t hplh - 38 50 - 60 ns delay matching: upper turn-off to lower turn-on t mon 1 8 - - 16 ns delay matching: lower turn-off to upper turn-on t moff 1 6 - - 16 ns either output rise time (10% to 90%) t rc c l = 1nf - 9 - - - ns either output fall time (90% to 10%) t fc c l = 1nf - 7.5 - - - ns either output rise time (3v to 9v) t r c l = 0.1 f - 0.3 0.4 - 0.5 s either output fall time (9v to 3v) t f c l = 0.1 f - 0.19 0.3 - 0.4 s minimum input pulse width that changes the output t pw ----50ns bootstrap diode turn-on or turn-off time t bs -10- - - ns isl2110, ISL2111
6 fn6295.1 july 11, 2006 timing diagrams pin descriptions symbol description v dd positive supply to lower gate driver. bypass this pin to v ss . hb high-side bootstrap supply. external bootstrap capacitor is r equired. connect positive side of bootstrap capacitor to this pi n. bootstrap diode is on-chip. ho high-side output. connect to gate of high-side power mosfet. hs high-side source connection. connect to source of high-side pow er mosfet. connect negative side of bootstrap capacitor to thi s pin. hi high-side input. li low-side input. v ss chip negative supply, which will generally be ground. lo low-side output. connect to gate of low-side power mosfet. epad exposed pad. connect to ground or float. the epad is electrically isolated from all other pins. figure 3. propagation delays figure 4. delay matching t hplh , t lplh t hphl , t lphl hi , li ho , lo t mon t moff li hi lo ho typical performance curves figure 5. isl2110 idd operating current vs frequency figure 6. ISL2111 idd operating current vs frequency 10 100 1 . 10 3 0.1 1 10 t = -40c t = 25c t = 125c t = 150c frequency (khz) iddo (ma) 10 100 1 . 10 3 0.1 1 10 t = -40c t = 25c t = 125c t = 150c frequency (khz) iddo (ma) isl2110, ISL2111
7 fn6295.1 july 11, 2006 figure 7. ihb operating current vs frequency figu re 8. ihbs operating current vs frequency figure 9. high level output voltage vs tempe rature figure 10. low level output voltage vs temperature figure 11. undervoltage lockout threshold vs temperature figure 12. undervoltage lockout hysteresis vs temperature typical performance curves (continued) 10 100 1 . 10 3 0.01 0.1 1 10 t = -40c t= 25c t = 125c t = 150c frequency (khz) ihbo (ma) 10 100 1 . 10 3 0.01 0.1 1 10 t = -40c t = 25c t = 125c t = 150c frequency (khz) ihbso (ma) 50 0 50 100 150 50 100 150 200 250 300 vdd = vhb = 8v vdd = vhb = 12v vdd = vhb = 14v temperature (c) vohl, vohh (mv) 50 0 50 100 150 50 100 150 200 vdd = vhb = 8v vdd = vhb = 12v vdd = vhb = 14v temperature (c) voll, volh (mv) 50 0 50 100 150 5.3 5.5 5.7 5.9 6.1 6.3 6.5 6.7 vddr vhbr temperature (c) vddr, vhbr (v) 50 0 50 100 150 0.4 0.45 0.5 0.55 0.6 0.65 0.7 vddh vhbh temperature (c) vddh, vhbh (v) isl2110, ISL2111
8 fn6295.1 july 11, 2006 figure 13. isl2110 propagation delays vs temperature figure 14. ISL2111 propagation delays vs temperature figure 15. isl2110 delay matching vs temperature figure 16. ISL2111 delay matching vs temperature figure 17. peak pull-up current vs output volt age figure 18. peak pull-down current vs output voltage typical performance curves (continued) 50 0 50 100 150 25 30 35 40 45 50 55 tlplh tlphl thplh thphl temperature (c) tlplh, tlphl, thplh, thphl (ns) 50 0 50 100 150 25 30 35 40 45 50 55 tlplh tlphl thplh thphl temperature (c) tlplh, tlphl, thplh, thphl (ns) 50 0 50 100 150 4 4.5 5 5.5 6 6.5 7 7.5 8 tmon tmoff temperature (c) tmon, tmoff (ns) 50 0 50 100 150 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 tmon tmoff temperature (c) tmon, tmoff (ns) 02 46 81012 0 0.5 1 1.5 2 2.5 3 3.5 vlo, vho (v) iohl, iohh (a) 02 46 81012 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 vlo, vho (v) ioll, iolh (a) isl2110, ISL2111
9 fn6295.1 july 11, 2006 figure 19. isl2110 quiescent current vs voltag e figure 20. ISL2111 quiescent current vs voltage figure 21. bootstrap diode i-v characteris tics figure 22. vhs voltage vs vdd voltage typical performance curves (continued) 0 5 10 15 20 0 10 20 30 40 50 60 70 80 90 100 110 120 idd ihb vdd, vhb (v) idd, ihb (ua) 0 5 10 15 20 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 idd ihb vdd, vhb (v) idd, ihb (ua) 0.3 0.4 0.5 0.6 0.7 0.8 1 . 10 6 1 . 10 5 1 . 10 4 1 . 10 3 0.01 0.1 1 forward voltage (v) forward current (a) 12 13 14 15 16 0 20 40 60 80 100 120 vhs to vss voltage (v) vdd to vss voltage (v) isl2110, ISL2111
10 fn6295.1 july 11, 2006 isl2110, ISL2111 dual flat no-lead plastic package (dfn) micro lead frame pl astic package (mlfp) top view index d1/2 d1 d/2 d e1/2 e/2 e1 e a 2x 0.15 b c a n bottom view seating plane 5 6 2 3 1 0.10 nx b a1 c 2x c 0.15 0.15 2x b 0 a1 a c c b 2x a c 0.15 a2 a3 area // side view 0.08 c 4x 9 l 5 nx b 4x p n e b 0.10 c a d2 e2 1 (nd-1)xe ref. 3 2 m 7 8 8 7 6 area index n-1 d2/2 nx k 5 e2/2 e for even terminal/side l c terminal tip c c l12.4x4a 12 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a - 0.85 0.90 - a1 0.00 0.01 0.05 - a2 - 0.65 0.70 - a3 0.20 ref - b 0.18 0.23 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc - d2 2.65 2.80 2.95 7, 8 e 4.00 bsc - e1 3.75 bsc - e2 1.43 1.58 1.73 7, 8 e 0.50 bsc - k 0.635 - - - l 0.30 0.40 0.50 8 n122 nd 6 3 p 0.24 0.42 0.60 - --12- rev. 0 8/03 notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. n is the number of terminals. 3. nd refer to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-vggd-2 issue c except for the l dimension .
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6295.1 july 11, 2006 isl2110, ISL2111 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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